Cadence System Design and Verification

By: Silicon Perspective  09-12-2011
Keywords: Assertion-based Verification

To boost verification productivity and enhance debug visibility, system design and verification teams require an assertion-based verification environment that unifies software, languages, IP, debug, and coverage. Cadence


assertion-based verification enables the detection of bugs close to the source during various design phases. Cadence technologies for simulation, acceleration, emulation, verification planning and management, comprehensive coverage, and formal verification enable assertion-based verification.

The Open Verification Library (OVL) and the Incisive Assertion Library are supported along with SVA and PSL languages in various Cadence Incisive


verification technologies. SVA and PSL can represent very complex temporal conditions in a concise manner and they work seamlessly in simulation, acceleration, and emulation. With broad support for industry-standard languages and libraries, Cadence assertion-based verification technologies help teams achieve verification completeness and measure it against comprehensive coverage. Assertions can also serve the purpose of documentation, which is helpful when reusing IP from one project to another.

Synthesizable testbenches and in-circuit emulation using

are common use modes when Palladium accelerators and emulators can be used. These use modes allow customers to run long system-level tests with high performance. Assertions are very useful during these long tests because they constantly monitor the design behavior, thus increasing debug productivity and the predictability of the design state.

Keywords: Assertion-based Verification

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