Cadence Logic Design

By: Silicon Perspective  09-12-2011
Keywords: Silicon

Silicon process-related phenomena combined with exploding SoC design complexity have introduced new transition-based defect types. As a result, engineers rely on more advanced—and often more expensive—at-speed or faster-than-at-speed test methodologies to ensure higher quality and profitability.

For successful SoC and analog/mixed-signal (AMS) design and test implementation, the need for predictability in both physical and test design flows is absolute. Integration of technologies that are conventionally standalone is essential for achieving concurrent optimization with meaningful correlation to downstream physical and test design flows.

Native to the Encounter RTL Compiler global synthesis environment, Encounter Test provides a unified platform that expands the definition of silicon quality to include area, timing, power, and testability. Encounter Test comprises three product technologies: Encounter DFT Architect, Encounter True-Time ATPG, and Encounter Diagnostics.

DFT Architect, combined with Encounter RTL Compiler, enables early and concurrent design-for-test (DFT) planning, testability, analysis, and verification. Links to Encounter True-Time ATPG achieves downstream correlation for greater predictability, the highest quality netlist, and fewer iterations for physical and test design flows. Encounter Diagnostics, with links to True-Time ATPG, provides the most accurate diagnostics solution available on the market for silicon bring-up, debug, and yield optimization. It delivers a comprehensive volume and precision diagnostics flow that ensures efficiency in yield learning and productivity in precision failure analysis.

Our Encounter Front-End Test Design and Diagnostics development teams have prioritized technology goals to include test quality, cost, and power—all facilitated through product integration—which boosts ease-of-use, productivity, predictability, and ultimately profit.

Keywords: Silicon

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