Cadence Functional Verification Flows

By: Silicon Perspective  09-12-2011
Keywords: Assertion-based Verification

Universal Verification Methodology (UVM)

An emerging Accellera standard for the expressed purpose of fostering universal verification IP (VIP) interoperability. Increases productivity by eliminating expensive interfacing that slows VIP reuse. Championed and supported by electronics companies throughout the verification ecosystem.

Open Verification Methodology (OVM)-based verification

Helps teams develop advanced verification environments with higher levels of integration and portability of verification IP. Fully open, supports multiple languages, and scales from block to system and project to project. Works seamlessly with the Cadence metric-driven verification flow and the Cadence

portfolio to maximize productivity, project predictability, and quality.

Metric-driven verification

Ensures verification project predictability, productivity, and quality. Uses specifications to create verification plans capturing verification intent, performs metrics analysis/reporting, measures progress, and automates verification tasks. Drives convergence toward verification goals and helps teams determine when high-quality verification is achieved. Uses the

and the Cadence

portfolio to simplify the adoption of metric-driven verification. Verifies designs at all levels of abstraction, from SystemC TLM to RTL to gates.

Low-power verification

Verifies low-power design intent without disrupting the functional verification environment. Integrates low-power verification planning, coverage, and debugging. Supports the Common Power Format (CPF).

Assertion-based verification

Allows teams to start verification earlier and remove bugs faster. Captures design intent, detects errors close to the source, provides coverage information, and enables formal analysis. Supports industry-standard languages. Includes unique assertion-based

to simplify adoption of assertion-based verification.

Mixed-signal verification

Cadence has introduced a mixed-signal verification (MSV) flow for digital-centric designs. The flow enables high-performance mixed-signal verification very close to digital speeds, and it can be used for high-volume regression testing. The CadenceĀ® MSV flow leverages real valued modeling (RVM) for top-level verification of analog or mixed-signal designs. Using the Cadence MSV flow, engineers can enhance the top-level verification performance of the overall verification process.

Keywords: Assertion-based Verification

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