3D-ICs with through-silicon via (TSV) pack a great deal of functionality into small form factors, while improving performance and reducing costs. 3D-IC packages also accommodate multiple heterogeneous die, such as logic, memory, analog, RF, and micro-electrical mechanical systems (MEMS). And since 3D-ICs support various process nodes, such as 28nm for high-speed logic and 130nm for analog, developers have the flexibility to place in a single package all of the functionality they want without requiring an expensive move to a new process node.
Cadence® stacked-die technology offers an automated 3D-IC/TSV design methodology integrated with implementation, extraction, and analysis tools. It captures design intent upfront, so users can pass design intent seamlessly throughout the flow. It then abstracts physical information to help users optimize 3D floorplanning and placement across multiple heterogeneous die, IC package, and board. Tight links to Cadence
(SiP) design environments to allow for continuous convergence, ensuring a manufacturable packaging solution. Robust thermal analysis and power management capabilities support design closure; TSVs and the ability to implement silicon interposers support both intermediate and long-term design needs.