In the chart shown below, the material limits, 20V/µm for Si, 220V/µm for SiC and 300V/µm for GaN, are compared with the actual results described in various published refereed papers. In the case of the GaN Systems devices these results are calculated based on the additional gate width achieved by our unique island topology, described in our provisional patents. It is clear from both the Si and SiC results that these technologies are at or near their technology limit in the case of the simpler field effect structures.
The GaN limit however remains ahead of what has been achieved by GaN in practice. While our calculated results are two orders of magnitude better than the Si devices, they are not yet close to approaching the GaN limit. GaN devices are at a very early stage of development, compared to the 30 years of power device development of Si and 20 years of SiC. We expect there will be a five times improvement over the next five years and GaN transistors will achieve specific on-resistance results better than 0.6 milliohm.cm.sq. This equates to a 30A/600V transistor (1cm.sq.) dissipating less than 1 Watt !
Our demonstration kit will provide devices that operate in the range 100-200V/60A and 600-1,000V/20A. These designs achieve a Wg of 6 meters and 2 meters respectively when scaled to a 1cm.sq. device.
The devices shown are symetrical and offset gate, normally-on and normally-off, triode and tetrode transistors.