RHEIMS (Rapid Hierarchical Energy Investigation Modelling System) is a comprehensive Transactional/SystemC power analysis tool. It is an innovative extension to the ENiGMA gate-level system and permits detailed system-level power analysis in the entire design cycle from concept (transactional) proto-type through RTL to gate-level pre and post place-and-route. It is unique in that it delivers comprehensive power analysis from the early to late stages of the design cycle.
- Power reduction up to 75% in designs through the novel experiential design concept.
- System-level Embedded code driven power analysis.
- A intuitive and easy to use system-level power analysis tool.
- A shorter design cycle through faster optimal design selection.
- Three orders of magnitude faster but within 1.5% accuracy of gate-level power estimation.
The RHEiMS-Instruction Set Simulator (ISS) solves one of the main challenges confronting programmers and
designers of embedded systems — the rapid and accurate system-level determination and analysis of the code
performance on a target processor.
The RHEiMS-ISS simulator takes the application source-code (typically C-code), compiles the code taking into
account any compiler optimisations, and then simulates the code on any one of a range of processors selected
by the user. Pipelining and cache effects of the specific processor are incorporated into the simulation.
- Execution speed is 3 orders of magnitude faster than conventional ISS.
- All compiler optimisations, pipeline and cache memory effects are accommodated in the analysis.
- The GUI is simple and straightforward.
RHEiMS-OPSL is an extension tool to the RHEiMS design flow. The power profiling generated by RHEiMS gives a very
detailed and accurate account of the component activity in the system-level design, their power consumption and that of
the entire system, and the duration of their activity. The RHEiMS-OPSL tool uses this profiling information to automate
the process of determining the optimum operating conditions for the system-level design, subject to minimising power
and/or execution time of the various modules and/or the number of voltage levels (islands) incorporated into the design.
In this process, the user has the choice of selecting which of these operating conditions will be optimised and the
constraints on one or more modules. Constraints typically define the min/max operational voltage and frequency of a
module, and the times of the tasks performed by the modules. Various slow/fast optimisation strategies incorporated into
the optimiser tool can also be selected by the user.
- Optimisations are generated from system-level profiles that can involve the execution of application s/ware
over extensive simulation time-frames. Thus, the optimisations are guaranteed to improve the general
performance of the design.
- The identification of the optimal operating conditions can be used to guide the design development from the
system-level through to behavioral and gate-level.
- Optimisation uses the RHEiMS platform ensuring system-level speed and gate-level accuracy.
The power-models that are produced by the system-level RHEiMS tool can also be integrated into normal RTL-level
simulations and used for cycle-based power analysis. Due to the different simulation environment only cycle-based or
data-driven cases in the RHEiMS power-model database are appropriate. The speed performance of power
estimation at this level of RHEiMS-PRTL is determined by that of the RTL simulation, since identically to system-level
RHEiMS, it operates within the context of the normal simulation platform.
- RTL power estimation two orders of magnitude faster but within 1.5% accuracy of gate-level power estimation.
- Power optimisation of a system-level design that can reduce power consumption by a further 20%.
- An easy, rapid and accurate power assessment environment for RTL designs.
The Power Tool delivers accuracy and speed for digital circuit power analysis. Power is calculated from a Verilog gate level netlist annotated with the power characteristics of the design’s target cell library. Both Dynamic, Toggle and Static (Leakage) power can be incorporated into the analysis. The tool is used at the gate level, with or without wire loading information derived from initial global placement of the circuit’s modular blocks. When a particular design has been placed and routed, more detailed and accurate analysis can be performed with the tool.
- Cycle accurate power estimation on a cycle by cycle basis can be rapidly generated and accessed.
- As circuit size increases, relative to other gate-level power estimation tools, ENiGMA’s processing
speed attains 2 orders of magnitude.
- Power/Energy dissipation can be analysed through the module hierarchy.