As is the case with any test methodologies, board and system test based on JTAG/Boundary Scan requires some Design for Testability (DFT).
For example, all devices featuring a JTAG compliant Test Access Port (TAP) should be linked up
in one or more scan chains that are accessible, ideally through a connector.
Under certain circumstances it may be desirable to configure the Unit Under Test with multiple
scan chains, in other cases just one chain may be beneficial.
Certain types of Boundary Scan test applications demand their own set of DFT rules.
The point is, the board/system designer is in charge of making the Unit Under Test Boundary Scan testable.
It is highly recommended to involve test engineers in design reviews in order to ensure a
comprehensive test strategy can be implemented.
GOEPEL can provide Design for Testability guidelines and even offers DFT analysis for Boundary Scan free of charge.
IEEE Std 1149.1 requires that vendors of Boundary Scan compliant devices provide so called BSDL files.
BSDL (Boundary Scan Description Language) files yield details about the test resources implemented in such a
device and are used by practically all Boundary Scan tools. Even though most BSDL files are correct these days,
there is always a chance of a syntax error or, worse, a description error (for example a specification of fewer
Boundary Scan cells than physically implemented in the chip, wrong instruction op-codes, or a wrong order of
Boundary Scan cells). The execution of Boundary Scan tests that have been generated based on incorrect BSDL files
will result in false diagnostics and, in the worst case, has potential to cause damage on the Unit Under Test.
GOEPEL offers as well as .
Training and Seminars
Boundary Scan technology is continuously evolving. The IEEE 1149.1 standard provides the specification for
respective test resources on digital I/O pins in compliant devices. Newer standards,
such as IEEE 1149.4 and IEEE 1149.6 define test resources for analog and mixed signal pins and for
high speed I/O pins, respectively. And a number of standardization efforts related to JTAG / Boundary Scan
have recently been completed (e.g. IEEE 1149.7, IEEE 1500) or are under way (e.g. IEEE P1149.8.1, IEEE P1581, IEEE P1687, SJTAG).
An Unit Under Test will always include some non-Boundary Scan circuitry, though (devices that do not implement
any of these test resources), such as simple buffers, memory devices, or glue logic and interface circuits,
just to name a few. Another application of Boundary Scan is the on-board and in-system programming of
programmable devices such as Flash EEPROM, serial EEPROM, PLD and FPGA devices. In recent years, the utilization
of on-chip emulation resources for board and system level test applications has become popular, too.
GOEPEL's SYSTEM CASCON Boundary Scan software suite provides all the tools needed to develop any such test and
GOEPEL offers a variety of seminars and training programs covering Boundary Scan technology and
GOEPEL Boundary Scan tools.
are offered as half day and full day events,
last from one day to four days, depending on the curriculum. Both, seminars and training classes can be customized to
cover specific topics and can be provided on-site for a corporate audience.
We also offer web based training (e-Learning) through Webinars and conference calls.
For a schedule of upcoming webinars, seminars, and training classes visit our page.
Or to request further information.