Multicore Performance Analysis
| How to predict performance of a multicore real-time embedded system? |
| Multicore Performance Analysis |
- Multicore real-time system architecting and optimization for performance, low-power and cost
System architects are in charge of making crucial decisions that impact the whole project. They analyze system specifications and make design choices in terms of system architecture, hardware/software partitioning and system dimensioning. Thanks to past experiences, they have built a strong expertise in their application domain and worked on various projects. Traditionally, architects have been relying on experience, spreadsheet calculations and "gut feeling" in order to establish new or derivative architectures.
Wrong architecture choices made very early can have dramatic consequences on projects. Systems are all different and increasingly complex, integrating new technologies and functions. It's more and more difficult to handle them without computer-aided modeling and simulation that give a dynamic view on systems that spreadsheets can't deliver. In addition, system architects deal with two distinct but complementary parts, hardware and software, usually developed by two separate teams, with their own practices and tools. As architects pass on their work to engineers who develop the system, the probability that designers introduce errors or deviate from the original vision is high. Explicit and complete executable specifications that can be easily shared and analyzed, with test cases that can be reused to validate the design, ensure correct interpretation and implementation of the design intent.
- Improving productivity
- Simplifying multicore application decomposition
- Processes and inter-process communications & synchronization
- Graphical model = implementation blueprint
- Guiding embedded designers
- Providing execution time budgets for algorithms development
- Reducing risks
- Avoiding potential real-time problems ahead-of-time
- Even before HW and SW availability
- Deadlocks, race conditions, CPU starvation, etc.
- Reducing project cancellations and delays
- Optimizing end-product
- Flexible architecture exploration free of any limitations
- Finding optimal architecture for parallel execution
- Tasks allocation, CPU loads, communications topolgy
- Tradeoff between performance and other requirements
- Memory footprint, power, cost
Low-power is the #1 challenge of embedded devices and chips design, for technical and business but also environmental reasons. New designs, in all application domains, have to be optimized for low power or they will fail. Unfortunately, power issues are too often passed-on from one stage of the design to the next, until physical designers hit the wall. In addition, power modeling and analysis is usually done separately from other design aspects: functionality, timing, performance, cost, area.
It's proven that power optimization has the largest impact at the architectural design stage, by far. 80% of total power optimization can be achieved at the architecture stage, while all other stages (system design, IC design, physical design) only count for 20% of potential power optimizations altogether. The power impact from one high-level architecture to another, including HW/SW partitioning, can be as much as 10 to 20x.
In addition, system architecting is efficient only if design parameters are taken into account all at once. Optimizing power separately from performance, cost or area doesn't make sense. Meeting the power specification but missing the timing requirements or not being able to deliver the expected functionality doesn't work either.
CoFluent Studio is the only system-level environment that allows users to create and simulate models including all aspects of the design: behavior, time budgets, application & platform architecture, HW/SW partitioning, interfaces, multicore & multitasking, communications & topologies, performance (latency, bandwidth), load (resource utilization ratio), cost, memory footprint, and power requirements. It allows users to associate static (representing powered-on needs + leakage) and dynamic (when a component is running) power laws to any application or platform-level activity (computation or communication) and component, and to partition the architecture into different power islands/domains. As the model provides a complete and dynamic picture of the system's structure and execution, power laws can be defined as simple C equations based on any other design parameters such as the load, speed or state of any element. More complex power models, either proprietary or computed through third-party tools, can also be plugged into the simulation through a dedicated API. Then CoFluent Studio computes all power laws step by step during simulation and is capable of giving a complete view of the system's power activity, globally or for each constituting element, including min, max and average power consumption values and dynamic power consumption profiles (against simulation time).