High definition low light NIR camera (2006-2007)
Developed the world's first back-illuminated CMOS camera optimized for near-infrared (NIR) response and is ideally suited for low light NIR imaging applications including microscopy, hyperspectarl imaging, biometrics, medical imaging, and surveillance.
· 1280 x 1024, 30 fps
· Flexible ROI settings
· CameraLink data port
A complete unit design was performed including:
Hardware architecture development,
Full set of real-time video processing algorithms: 3D adaptive noise reduction (DNR), piece-wise Gamma, and automatic self-adjustable histogram equalizer.
Verilog modules for large FPGA device using ActiveHDL, Synplify, Quartus (including Nios sort core processor),
Analog front-end including anti-aliasing filters, DC restore circuit, 16-bits ADC,
CameraLink video transfer interface and USB for ROI definition,
Win32 application for ROI definition with user-friendly GUI.
LEDs-based video display processor ASIC (2006-2007)
Developed a LED-based video display processor including general concept, hardware architecture, distributed network fundamentals; and finally a pure Verilog synthesisable ASIC code was delivered.
In progress of development a few innovations were discovered: highly effective video processing algorithm, adaptive Manchester decoding algorithm, and sophisticated automatic recovery circuit.
The development was including:
- Image visualization by distributed pixels network
- Image processing for outdoor video visualization
- Noise immune communication network including adaptive filtration and synchronization methods
Image processing for system testing and calibration.
Smart video surveillance system (2006)
Developed real-time FPGA-based video processing system including general concept, hardware architecture, software model, Verilog synthesisable code development, ORCAD schematic drawing, working prototype demonstration and full project documentation release.
In progress of development a few innovations were discovered:
Objects detection for very hard outdoor condition (wind, cloud, rain, fog, etc.) by using 3-D adaptive filtration methods.
- Objects tracking, by objects color tone, texture, and shape analysis.
Objects recognition (human-animal-vehicle) was based on collecting information (properties) for each object, building objects properties data-base, data-base records analysis including objects cross-influence.
HDTV real-time video improvement processor
FPGA-based video processing system for large size LCD/Plasma displays including:
- Highly effective Adaptive 3-D noise reduction algorithm;
- MPEG/H.xxx compression artifacts reduction by adaptive non-linear 3-D image processing;
- Adaptive local and integral non-linear transform: gamma, histogram equalization;
- Sharpness enhancement without "ringing effect";
- full real-time FPGA/ASIC based approach for 720p, 1080i, and 1080p video modes.
Development was included a general concept, hardware architecture, software model, Verilog synthesisable code for Altera, Xilinx FPGAs, and ASIC, OEM board development and production, and full project documentation release.
Piece-wise non-linear video transform (2007)
Highly effective algorithm (based on well-known piece-wise approach) has been developed for real-time FPGA/ASIC platform. Only a single multiplier, adder, and some minor logic modules is require to perform such 10-bits real-time video transformations as: gamma, histogram stretching/compression, etc.
Highly effective color space conversion (2007)
Highly effective algorithm for real-time FPGA/ASIC platform. Only a single multiplier, adder, and some minor logic modules is require to perform such 10-bits precision real-time video color space conversion RGB->YCrCb, and YCrCb->RGB.
Pipelined 3-D adaptive video filter (2006)
Highly effective algorithm for real-time FPGA/ASIC platform including SDRAM-based temporal (frame-by-frame) recursive (IIR) video filter with tunable recursive coefficient, and 2-D Finite Impulse Response Gaussian filters.
Distributed multi-drop communication network simulation model software application (2007)
Developed for BER (Bit Error Ratio) estimation of complex multy-drop bidirectional communication network. The software generator was capable to produce Verilog simulation vectors file containing Manchester-coded signal with user defined calibrated noise, jitter, and echo artifacts.