Vital-Sim Logic Simulator
VSLS is a WINDOWS® 2000/XP based software and graphics package which allows signal engineers to test vital and non-vital application logic programs generated by a wide variety of development systems. At present, VSLS is capable of Microlock I & II /Genisys®, VPI/CSEX®, VHLC and ALC®, Microtrax® and Electrocode/Electrologic® programmable devices. VSLS includs Layout Screen Customizer and Relay Equivalents capabilities.
VSLS can operate with one monitor display on any computer that supports Windows 98®, Windows NT®, Windows 2000®, Windows XP® and Windows 7 Professional® software. For improved efficiency and effectiveness, operating VSLS on multiple screens is recommended but appropriate video drivers are required for multiple displays.
Screens are configured by the user and most often feature a combination of track and signal layout and circuit nomenclature lists that include tag names or input, output and internal variable names.
Unlike other simulators, VSLS permits simultaneous testing of both vital and non-vital programs for a location, as well as any slave vital units or external relays and line wire interconnections in the interlocking scheme. this feature helps insure that individual programs execute properly as well as insuring that the communication between units is correct, eliminating a major stumbling block that occurs during cutovers.
Because signal engineers can use VSLS to test all elements of the location simultaneously and because signal engineers can test virtually all aspects of the programs, they can complete an intergrated operation simulation on the logic long before the cutover time, debugging logic equations on the go more effeciently and effectively that any other method. Shop and in-service testing can then be concentrated on checking for wiring errors.
NOTE: VSLS is not substitute for competent signal engineering knowledge. The user of VSLS must understand the train and signal operating sequences that require checking and the methods used to achieve the sequences. The VSLS requires the user to manually activate all inputs (e.g. switch positions, coded circuits inputs, control office commands, track circuit sequences, etc.) and he must be able to recognize when an improper or unsafe result has occurred.
Another common application of the VSLS is training. Using the Simulator’s capability to display relay logic equivalents of the logic equations provides the means to demonstrate logic formulas in graphic form. Because the display is active, it actually provides the means to show how the signal circuit works. This feature is particularly helpful in training inexperienced circuit designers or designers not familiar with programming of solid state interlocking devices. Personnel responsible for installation of the solid state interlocking devices are also able to train for the cutover by running the software in advance.
Proving out of relay-based interlocking systems, or revisions to such systems, can al be accomplished by writing equivalent logic formulas, compiling them with a vendor complier of a choice, then running them on the VSLS. Toggling to the relay-equivalent display when a false response occurs enables the signal designer to see his mistake. Simulator Operation
After using the software supplied by the vendor of the solid state interlocking device to write and compile the device operating system program , the interpreter section of the Vital Signal Logic Simulator copies and reads the Boolean or Equivalent Circuits text file , strips out any unnecessary parts and rearranges the I/O bits and variables in alphabetical and numerical order. A user-friendly graphics utility allows the signal designer to draw the track and signal diagram using basic building blocks , then assign input and output bits to the various components. The result is a Boolean simulator that allows the user to see the status of all the inputs/outputs , internal variables , timers , track circuit status and signal aspects at the same time. Nomenclatures appear adjacent to their respective icons.
Once the interface (circuit nomenclature) information has been established , the signal designer may use a mouse to select and toggle input bits. The actual Boolean logic program runs in the background and will display any changes to variable or output bits and also updates the track and signal graphic with such information as track occupancies and changes to signal aspects , switch positions , HD line circuits , code rates , etc. As individual bits are selected , the logic equations related to the bits are displayed at the top of the screen. If an improper response to a control function occurs , the erroneous Boolean equation is readily visible for immediate analysis and appropriate corrective action.
An additional feature of the basic VSLS package is the automatic , relay equivalent conversion graphic display of Boolean formulas. The display is active (permitting use of the mouse to change the status of relays shown) permitting visual review of all circuit activity. As test are made , active Boolean formulas are displayed and relay equivalents respond appropriately. Electric current flow on the appropriate path through contacts , to a particular relay coil , is indicated by a change in color of the connecting line ("wire") and relay icon.
Recent enhancements expand the application of VSLS beyond proving the correctness of software. The optional Lamp Out and Route Locking List Generators automatically provide cutover lists that historically have been generated by a combination of the cut-and-paste method and the mental alertness of the designer producing the lists. In the case of the Route Locking List Generator, pictorials of each route can be printed to assist with the checking and analysis. These programs provide very beneficial capabilities by substantially reducing the pre-cutover workload and assuring the validity and completeness of cutover safety checks